Representing the internal SOC (system-on-chip) interface for the purpose of emulation is generally done by exposing one or more of the internal SOC buses, allowing system engineers to extend the emulation part utilizing external FPGA (field programmable gate array). While this approach is useful for most of the cases, it does not allow exposure of all the required interfaces for a complete and accurate emulation. Due to a limited pin count, a majority of the IC designs allow only some of the interfaces to be exposed (or some of the interfaces may be multiplexed into a unified exposed interface).
To overcome the shortcomings of limited interface exposure via the emulation device I/O, and to verify a designed circuit more accurately, prototyping technologies based on hardware emulation for verifying a designed circuit are highly pursued because hardware emulation is closer to the actual digital circuit. In a general prototyping system based on hardware emulation, the digital circuit for verification may be implemented in the prototyping engine which is composed by interconnecting reusable field programmable devices (RFPDs) and other discrete devices such as microprocessors, digital signal processors, application specific non-memory devices or memories. A RFPD includes FPGA, programmable logic device (PLD), and the like. RFPDs have been frequently used in prototyping since a digital circuit may be implemented in the RFPDs by being simply programmed onto the RFPDs, and further, the RFPDs may be reused.
Recently a semiconductor device called “slice” (e.g., RapidSlice™ developed by LSI Logic Corporation, and the like) has been developed. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers to be completed with the customer's unique IP (intellectual property). The slice may include pre-diffused IP blocks such as memory, microprocessors, PCI-X controllers, and the like that suit the slice to a given target market, and an area of customizable logic where the customer logic may be implemented using the metal layers. A shell, i.e., some logic infrastructure, may personalize one or more pre-diffused IP blocks as an IP Subsystem. Such an IP subsystem may represent an integrated design, which includes one or more pre-diffused IP blocks and the associated shell. Each subsystem of the slice may have a SOC interface that permits the designer to interface and utilize the subsystem as part of the area of customizable logic.
A slice may enhance the efficiency of IC design since the slice may provide a designer with ready-made pre-diffused IP blocks in the slice. For example, when an IC designer needs to include an ARM microprocessor in a product, the designer may prefer to utilize a ready-made pre-diffused ARM microprocessor in a slice for prototyping rather than incorporating such an ARM microprocessor within the customized logic. However, there is a practical difficulty in this approach because the pre-diffused IP blocks (e.g., the ARM microprocessor) in the slice are typically not exposed for prototyping—the interface pins of the pre-diffused IP blocks are not normally accessible form outside the slice.
Therefore, it would be desirable to provide a method and apparatus for exposing all required pre-diffused IP blocks or IP subsystems, in a semiconductor device for the purpose of accurate prototyping based on hardware emulation.